The present invention relates to a method of fabricating a semiconductor device, or in particular to a technique of reducing the surface misalignment in flattening an insulating film by the CMP (chemical mechanical polishing) process in the STI (shallow trench isolation) method for dividing the surface of a semiconductor substrate into regions by grooves.
The STI method is used to separate semiconductor devices through the process of forming grooves (region dividing grooves) for dividing the surface of a semiconductor substrate into regions, forming an insulating film on the surface of the semiconductor substrate including the interior of the region dividing grooves, and flattening the insulating film.
In the STI method, it is crucial to flatten the divided regions without adversely affecting the surface of the semiconductor substrate in the flattening process. The CMP process is a flattening method which has recently found applications.
FIG. 16 is a diagram for explaining the steps of a method of fabricating a semiconductor device according to the prior art.
The surface of a semiconductor substrate 10 shown in FIG. 16A is formed with region dividing grooves 10a shown in FIG. 16B, so that the substrate 10 is divided by the grooves 10a into a first region Aw which is an active region having a relatively large area and a second region An which is an active region having a relatively small area. Next, as shown in FIG. 16C, an insulating film (oxide film) 11 is formed on the substrate 10 including the interior of the grooves 10a. The insulating film 11 assumes the state buried in the grooves 10a. 
Next, as shown in FIG. 16D, the insulating film 11 is covered with an etching mask 12 having a single opening pattern 12c at a position corresponding to the first region Aw. The position of the opening pattern 12c corresponds to that of the insulating film 11w on the first region Aw. The part of the first region Aw where the mask 12 is superposed on the insulating film 11w is designated by Dw.
Under the condition shown in FIG. 16D, the insulating film 11 is etched using the mask 12, and an assembly shown in FIG. 16E is formed. Specifically, only the part of the insulating film 11w of the first region Aw at a position corresponding to the opening pattern 12c of the mask 12 is etched. The etched part is limited to the insulating film 11w on the first region Aw. The part of the insulating film 11w at a position corresponding to the opening pattern 12c is etched off to form an opening 11q. Reference numeral 11w1 designates the remaining part of the insulating film at a position corresponding to the superposed region Dw.
Under the condition shown in FIG. 16E, the insulating film 11 is removed from the surface of the substrate 10 by the CMP process. Specifically, the insulating film 11n on the second region An and the remaining part 11w1 of the insulating film on the first region Aw are removed to achieve the state in which the insulating film 11 is buried only in the grooves 10a, as shown in FIG. 16F. The insulating film buried in the grooves 10a constitutes buried insulating films 11u. 
Ideally, the upper surface of each buried insulating film 11u and the upper surface of the substrate 10 are flattened in a flush state with each other.
In the prior art, the process of etching off the insulating film is aimed only at the first region having a relatively large area. Specifically, the insulating film in the second region having a relatively small area is not removed. As a result, in the next CMP process, the presence of the insulating film lacks uniformity, and a large misalignment develops between the surface of the insulating film in each dividing groove and the surface of the semiconductor substrate.
In forming the gate electrode of a transistor, for example, a large surface misalignment causes the thickness irregularities of the polycrystalline silicon film formed on the semiconductor substrate. As a result, an etching residue is liable to remain on the polycrystalline silicon film. Inconveniently, this residue often causes the shorting between the gate electrodes or between the gate electrode and other wiring layers.
In the case where the CMP process is executed to avoid this inconvenience with the insulating film set to the same surface height as the semiconductor substrate, an overpolishing develops locally. Then, the characteristics of the semiconductor device formed in the active region are adversely affected.